College of Engineering

A Master thesis was discussed in Department of Architecture Engineering / College of Engineering / University of Mosul entitled “The Architecture Design of Forward Error Correction Type Low Density Parity Check” on Sunday, Sep. 5, 2021, submitted by postgraduate student (Arwa Hafidh Ali).The thesis aims to design LDPC architectures in transmitter and receiver using Vivado High-Level Synthesis (HLS) and C++ programming language based on Field-Programmable Gate Array (FPGA). Likewise, it has applied Zynq-7000 hardware to implement the Vivado HLS designs. Moreover, reliable communication over the noisy channel has been implemented by the hardware of LDPC code.The thesis dealt with design and apply LDPC encoder, Bit Flipping (BF) decoder, and Min Sum (MS) decoder to investigate various parameters, such as the latency, the estimated time and the throughput. Not only that, but also, a mixed decoder model has been proposed, designed and implemented based on a merging of BF and MS algorithms. As well as, proposing to apply some optimization methods such as Array partitioning and Loop unrolling on all designs.The results showed an improvement in the obtained measurements, including an increase in the speed of implementation, decrease in the latency, enhancement in throughput and an improvement in hardware parameters in general.